The simplest CMA structure using IGFETs is probably the one which uses first and second similar IGFETs having respective drain electrodes respectively connected to input and output terminals for the CMA, having respective source electrodes connected to a common terminal for the CMA, and having respective gate electrodes that have a point of interconnection between them. The first IGFET is provided drain-to-gate feedback by a connection from the input terminal of the CMA to the point of interconnection between the gate electrodes of the first and second IGFETs. The IGFET is a charge-controlled device, rather than a current-controlled device like the bipolar transistor. Accordingly, there is no static feedback current error in this CMA structure using IGFETs, as contrasted to a structurally similar CMA using bipolar transistors.
In this simplest CMA structure the first IGFET is a "master" transistor, having its source-to-gate potential self-regulated by its drain-to-gate feedback connection; and the second IGFET is a "slave" transistor having its source-to-gate potential regulated together with the source-to-gate potential of the "master" transistor. The IGFET is normally more subject to Early effect than the bipolar transistor, so in a CMA using IGFETs as "master" and "slave" transistors quite often the "slave" transistor is used as the common-source amplifier transistor followed by a common-gate amplifier transistor in a cascode output stage. Even in more complex CMAs using IGFETs, though, one can identify a "master" transistor adjusted by feedback to conduct the CMA input current and a respective "slave" transistor adjusted in accordance therewith for conducting each CMA output current ratioed to the CMA input current.
The IGFETs used in CMAs are enhancement-mode transistors, so the slave IGFETs can be removed from conduction, or "cut off". The matching or ratioing of the channel current versus source-to-gate potential characteristics of the master and slave IGFETs tends to be better as the devices are made more enhancement-mode or remote-cut-off in nature. Close matching or ratioing of these characteristics is the sine qua non for good current mirror operation. As the master and slave IGFETs in a CMA are made more enhancement-mode or remote-cut-off in nature, the threshold voltage V.sub.T, or source-to-gate potential required to sustain appreciable conduction through the channel, rises to at least a volt and often a few volts. In the simplest CMA structure using IGFETs, as described above, increasing V.sub.T increases the input potential between the common and input terminals that is required for CMA operation. Generally, increases in the input potential between the common and input terminals of CMAs using IGFETs as master and slave devices, in order for CMA operation to obtain, are noted as V.sub.T increases for these devices. CMA input potentials of a volt or more generally are not of major concern in IGFET integrated circuits using supply voltages of 5 volts or more, although the number of current-mode stages that can be stacked up between supply rails is reduced, tending to require additional current paths between supply rails and to cause undesirable additional power consumption. CMA input potentials of more than a volt or so cannot be tolerated in IGFET integrated circuits using lower supply voltages (e.g., of 3 volts or so). IGFET integrated circuits using supply voltages of 3 volts or less are gaining the attention of electronic designers especially for battery-powered equipment.
U.S. Pat. No. 3,953,807 issued 27 April 1976 to O. H. Schade, Jr., and entitled "CURRENT AMPLIFIER" is incorporated herein by reference. FIG. 1 of the drawing of U.S. Pat. No. 3,953,807 shows an all-IGFET current mirror amplifier, with first and second IGFETs in cascode connection with each other in the input stage, and with third and fourth IGFETs in cascode connection with each other in the output stage of the CMA. The first and third IGFETs are in common-source-amplifier connections in their respective cascode connections with their drain electrodes connecting to the source electrodes of the second and fourth IGFETs, respectively; and the gate electrodes of the first and third IGFETs are biased by direct feedback connection from the drain electrode of the first IGFET. The second and fourth IGFETs are in common-gate-amplifier connections in their respective cascode connections with their drain electrodes connecting to the CMA input terminal and to the CMA output terminal, respectively; and the gate electrodes of the second and fourth IGFETs are biased by direct feedback connection from the CMA input terminal. The input potential for this type of CMA is more than twice threshold voltage. Even with IGFETs that have V.sub.T s of only one volt or so, the input potential tends to exceed two volts.
U.S. Pat. No. 3,953,807 is evidence that there has been a longfelt desire to reduce the quiescent input and output potentials required for operation of CMAs using IGFETs in their construction. FIG. 2 of the drawing of U.S. Pat. No. 3,953,807 shows a modification of the CMA of FIG. 1 in which the self-biased second IGFET is replaced by a series connection junction diodes poled for forward conduction of current. The voltage drop across this series connection of junction diodes is lower than the source-to-gate voltage (V.sub.GS) of the self-biased IGFET, so the source follower action of the fourth IGFET places a source-to-drain (V.sub.DS) on the third IGFET that is smaller than its V.sub.GS. A cascode operated so the V.sub.DS of its common-source-amplifier transistor is less than its V.sub.GS is termed a "nested" cascode by transistor circuit designers. The voltage drop across this series connection of junction diodes being lower than the source-to-gate voltage (V.sub.GS) of the self-biased IGFET results in the input voltage of this CMA with "nested" cascode output stage being reduced if the V.sub.T s of the IGFETs is a few volts. With lower-V.sub.T IGFETs the series connection of junction diodes can be replaced by a single junction diode or possibly a series connection of Schottky-barrier diodes to get a CMA with input potential, only a few tenths volt more than the V.sub.GS of an IGFET that has a V.sub.T of only one volt or so. In certain circumstances, particularly in integrated circuits using supply voltages of 3 volts or less, it is desirable if the input potential of a CMA with "nested" cascode output stage can be still further reduced.
The CMAs with "nested" cascode output stages thusfar described are undesirable in that the bias diode(s) do not have an electrode in the substrate of an integrated circuit and so have to be fabricated in an isolated region of semiconductor. This is undesirable in certain fabrication technologies--e.g., complementary metal-oxide-semiconductor (CMOS) technology. An objective of the invention disclosed herein is to provide a CMA with IGFET nested-cascode input and output stages which CMA does not require in its construction a semiconductor junction that floats in potential respective to integrated-circuit substrate.
In FIG. 6 of the drawing of U.S. Pat. No. 3,953,807 Schade shows a CMA using IGFETs that has an input potential only a few tenths volt more than the V.sub.GS of an IGFET that has a V.sub.T of only one volt or so. In this CMA the gate electrodes of the first and third IGFETs are biased by direct feedback connection from the CMA input terminal. The gate electrodes of the second and fourth IGFETs are furnished a bias potential of about 1.5 V.sub.GS from a reference voltage circuit formed from a further IGFET in common-source-amplifier connection with drain-to-gate voltage feedback through a resistive potential divider. The bias potential of about 1.5 V.sub.GS appears across the input of the resistive potential divider connected between the source and drain electrodes of the further IGFET. An objective of certain embodiments of the invention disclosed herein is to provide a CMA with IGFET nested cascode input and output stages which CMA does not have to include a power-consuming reference voltage circuit or a resistive potential divider in its construction.
U.S. Pat. No. 4,260,946 issued 7 April 1981 to C. F. Wheatley, Jr., and entitled "REFERENCE VOLTAGE CIRCUIT USING NESTED DIODE MEANS" shows a cascode connection of IGFETs in which the common-source-amplifier IGFET and the common-gate-amplifier IGFET have respective channels with similar width-to-length (W/L) ratio, but have different doping of the semiconductor under their gate electrodes. Accordingly, for the same current flow through their respective channels the common-gate-amplifier IGFET has a smaller V.sub.GS than the common-source-amplifier IGFET has. This permits their gate electrodes to be connected together and biased by feedback from the drain electrode of the common-gate-amplifier IGFET. The feedback regulates the serial conduction, by the serially-connected channels of the IGFETs, of current applied between the source electrode of the common-source-amplifier IGFET and the drain of electrode of the common-gate-amplifier IGFET. The V.sub.GS of the common-gate-amplifier IGFET being smaller than the V.sub.GS of the common-source-amplifier IGFET provides for the common-source-amplifier IGFET having sufficient V.sub.DS for conduction through its channel.
In the book Analog MOS Integrated Circuits for Signal Processing, copyrighted 1986 by John Wiley & Sons, Inc., and edited R. Gregorian and G. C. Temes, subchapter 4.16 "High-Performance CMOS Op-Amps" describes circuitry for biasing IGFET cascodes. First and second bias-network IGFETs have respective channels with relatively large and relatively small W/L ratios, respectively, a 4:1 ratio being particularly described. Each of the first and second bias-network IGFETs has its source-to-gate potential V.sub.GS self-regulated by a respective direct drain-to-gate feedback connection without substantial intervening impedance to condition its channel for conducting a reference current, as separately applied Thereto. The first bias-network IGFET applies its V.sub.GS to determine the quiescent gate potential to the common-source-amplifier IGFET in the cascode as referred to its quiescent source potential, and the second bias-network IGFET applies its V.sub.GS to determine the quiescent gate potential of the common-gate-amplifier IGFET in the cascode, as referred to the quiescent source potential of the common-source-amplifier IGFET in the cascode.